1. Field of the Invention
The embodiments of the invention generally relate to analyzing signal processing systems and, more particularly, to signal timing and noise analysis in electronic circuits.
2. Description of the Related Art
Full chip timing is typically performed using static timing tools, one net at a time. In this regard, a net is generally defined as a collection of electrical terminals all of which are electrically connected to one another. Static timing analysis is generally an exhaustive technique of analyzing, debugging, and validating the timing performance of a particular chip design. Usually, this is achieved by breaking down the entire design into sets of electrical timing paths. The signal delay on each path in the design is calculated and checked against the known timing parameters for any possible violation. Often, a circuit is affected by various types of noise. A net that is affected by noise is known as a victim net, while the neighboring nets which affect a victim net are known as aggressor nets. Typically, both victim nets and aggressor nets may each be embodied as a simple, point-to-point circuit comprised of a source and a sink, or it may be a more complex circuit.
Generally, for these static timing tools to work properly and efficiently the nets have to be decoupled, such that each net can be timed using a timing methodology without prior knowledge of the specific switching of the other nets. Coupling capacitances between nets cause the switching aggressor net to transfer current into the victim net it couples to, which can be switching or quiet. In either case, the underlying assumption in the timing tool that these coupled nets are independent is not necessarily valid.
Conventional adjustments to the timing methodology have been created to analyze the impact of simultaneous switching. Moreover, it has been determined that it is advantageous to be able to focus on those particular nets which are most likely to cause a problem and not be concerned about good (i.e., properly functioning) nets. Typically, many signal coupled noise events, such as cross-talk noise, accumulate to result in chip failure. For example, in digital chips, excessive cross-talk noise on a victim net can lead to logic failure or chip timing failure. In this regard, cross-talk noise is the noise induced by the parasitic coupling between on-chip wires. Each coupled noise event has a certain probability of occurring. For the noise event to impact timing, the aggressor and victim nets have to switch in the same clock cycle. On average, every net switches every fifth cycle or earlier. The probability that all possible coupling interactions occur simultaneously, within one circuit path, becomes very small with many aggressors. Furthermore, the direction of each noise event (i.e., whether the noise accelerates or decelerates the signal transition) is also random, further reducing the combined effect of many noise events within a timing path.
Based on extracted parasitic data alone, chip designers working with noise analysis tools have to assume the worst-case scenario for setting up the analysis conditions. For example, the analysis conditions may include if, when, and in which direction a signal can switch. The most pessimistic assumption is that any aggressor net or problem-causing signal will switch, and at the worst possible moment, and in the direction that causes the worst possible noise. Conventional noise analysis applies pessimistic assumptions to every noise event, resulting in tens of thousands of failing slacks on good and working chips. Many of these failing slacks can be considered false due to this pessimism. In this regard, noise slack is defined as the noise margin at a sink minus the noise injected at that sink. A negative slack indicates the possibility of a functional failure at that net. For nets with multiple sinks, the sink with the smallest noise slack is reported in pessimistic assumptions. Thus, noise filters are essential for an acceptable static timing methodology. Conventional methods filter small coupling capacitors and noise events with small delay impacts. However, this approach can lead to failures for data buses when all coupled nets move together in phase. Then, even small coupling events add up quickly to impact significant noise-induced timing changes.
The probability distribution of delay impact of coupled noise (i.e., statistics) should, therefore, not only take into consideration the process tolerance impacting coupling capacitance and resistance and transistors, but also the circuit's tolerance to slew (i.e., noisy transition) and arrival time relations, as well as the logic circuitry's tolerance to switching direction and activity.
These statistics are modified by regular circuit designs, such as data buses in which the same logic flow forces all nets to switch together. Other exceptions include clock nets which exhibit very high activity, mostly switching with every cycle.
As such, a proper statistical treatment and analysis of coupled noise should preferably take these exceptions into account. Therefore, there is a need to provide a coupled noise analysis technique which accounts for various parameters presently unaccounted for in conventional techniques.